SI5338 Datasheet, PDF (102/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 112.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
MS1_PHOFF[14:8]
Type
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7
Reserved
Reserved
MultiSynth1 Initial Phase Offset.
6:0
MS1_PHOFF[14:8]
MultiSynth1_PHOFF[14:0] is a 2s complement number. The initial
phase offset is MultiSynth1_PHOFF[14:0] x Tvco/128 where Tvco is the
period of the VCO.
Register 113.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
MS1_PHSTEP[7:0]
Type
R/W
Reset value = xxxx xxxx
Bit
Name
Function
MultiSynth1 Phase Step Size.
The phase step size is MultiSynth1_PHSTEP[13:0] x Tvco/128 where
7:0
MS1_PHSTEP[7:0]
Tvco is the period of the VCO. Either the phase inc/dec pins (if avail-
able) or register 63[1:0] will control the stepping of phase. A phase
increment will delay the clock edge.
102
Rev. 0.6