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SI5338 Datasheet, PDF (164/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
Si5338
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
 CLKIN—single-ended clock input
 I2C_LSB—determines the LSB bit of the 7-bit I2C address
 FINC—frequency increment pin
 FDEC—frequency decrement pin
 PINC—phase increment pin
 PDEC—phase decrement pin
 FDBK—single-ended feedback input
 OEB—output enable
Table 18. Pin Function by Part Number
Pin # Si5338A: 710 MHz Si5338D: 710 MHz Si5338G: 710 MHz Si5338K: 710 MHz Si5338N: 710 MHz
Si5338B: 350 MHz Si5338E: 350 MHz Si5338H: 350 MHz Si5338L: 350 MHz Si5338P: 350 MHz
Si5338C: 200 MHz Si5338F: 200 MHz Si5338J: 200 MHz Si5338M: 200 MHz Si5338Q: 200 MHz
1
CLKIN1
CLKIN1
CLKIN1
CLKIN1
CLKIN1
2
CLKINB1
CLKINB1
CLKINB1
CLKINB1
CLKINB1
3
CLKIN2
PINC
FINC
OEB
CLKIN2
4
I2C_LSB
PDEC
FDEC
I2C_LSB
FDBK3
5
FDBK4
FDBK4
FDBK4
FDBK4
FDBK4
6
FDBKB4
FDBKB4
FDBKB4
FDBKB4
FDBKB4
7
VDD
VDD
VDD
VDD
VDD
8
INTR
INTR
INTR
INTR
INTR
9
CLK3B
CLK3B
CLK3B
CLK3B
CLK3B
10
CLK3A
CLK3A
CLK3A
CLK3A
CLK3A
11
VDDO3
VDDO3
VDDO3
VDDO3
VDDO3
12
SCL
SCL
SCL
SCL
SCL
13
CLK2B
CLK2B
CLK2B
CLK2B
CLK2B
14
CLK2A
CLK2A
CLK2A
CLK2A
CLK2A
15
VDDO2
VDDO2
VDDO2
VDDO2
VDDO2
16
VDDO1
VDDO1
VDDO1
VDDO1
VDDO1
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
164
Rev. 0.6