C8051F99X_10 Datasheet, PDF (70/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V_REF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V_REF x 2.
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V_REF
voltage, or to measure input voltages that are between V_REF and V_DD. Gain settings for the ADC are
controlled by the AMP0GN bit in register ADC0CF.
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
5.4. 12-Bit Mode (C8051F980/6 and C8051F990/6 devices only)
C8051F980/6 and C8051F990/6 devices have an enhanced SAR converter that provides 12-bit resolution
while retaining the 10- and 8-bit operating modes of the other devices in the family. When configured for
12-bit conversions, the ADC performs four 10-bit conversions using four different reference voltages and
combines the results into a single 12-bit value. Unlike simple averaging techniques, this method provides
true 12-bit resolution of AC or DC input signals without depending on noise to provide dithering. The
converter also employs a hardware Dynamic Element Matching algorithm that reconfigures the largest
elements of the internal DAC for each of the four 10-bit conversions to cancel the any matching errors,
enabling the converter to achieve 12-bit linearity performance to go along with its 12-bit resolution. For
best performance, the Low Power Oscillator should be selected as the system clock source while taking
12-bit ADC measurements.
The 12-bit mode is enabled by setting the AD012BE bit (ADC0AC.7) to logic 1 and configuring Burst Mode
for four conversions as described in Section 5.2.3. The conversion can be initiated using any of the
methods described in Section 5.2.1, and the 12-bit result will appear in the ADC0H and ADC0L registers.
Since the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is
4 x (1023) = 4092, rather than the max value of (2^12 – 1) = 4095 that is produced by a traditional 12-bit
converter. To further increase resolution, the burst mode repeat value may be configured to any multiple of
four conversions. For example, if a repeat value of 16 is selected, the ADC0 output will be a 14-bit number
(sum of four 12-bit numbers) with 13 effective bits of resolution.
5.5. Low Power Mode
The SAR converter provides a low power mode that allows a significant reduction in operating current
when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit
(ADC0PWR.7) to 1. In general, low power mode is recommended when operating with SAR conversion
clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on power
consumption and the maximum clock frequencies allowed in each mode. Setting the Low Power Mode bit
reduces the bias currents in both the SAR converter and in the High-Speed Voltage Reference.
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