C8051F99X_10 Datasheet, PDF (106/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
SFR Definition 8.1. CS0CN: Capacitive Sense Control
Bit
7
6
5
4
3
2
1
0
Name CS0EN CS0EOS CS0INT CS0BUSY CS0CMPEN Reserved CS0PME CS0CMPF
Type R/W
R
R/W
R/W
R/W
R
R
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB0
Bit
Name
Description
7
CS0EN CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
6
CS0EOS CS0 End of Scan Interrupt Flag.
0: CS0 has not completed a scan since the last time CS0EOS was cleared.
1: CS0 has completed a scan.
This bit is not automatically cleared by hardware.
5
CS0INT CS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
4 CS0BUSY CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
3 CS0CMPEN CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator enabled.
2
Reserved Read = Varies.
1
CS0PME CS0 Pin Monitor Event.
Set if any converter re-tries have occurred due to a pin monitor event. This bit
remains set until cleared by firmware.
0 CS0CMPF CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
106
Rev. 1.0