C8051F99X_10 Datasheet, PDF (155/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
14.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V_DD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the V_DD Monitor must be enabled and
enabled as a reset source on C8051F99x-C8051F98x devices for the Flash to be successfully modified. If
either the V_DD Monitor or the V_DD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
14.5.1. V_DD Maintenance and the V_DD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum V_DD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external V_DD brownout circuit to the RST pin of the device that
holds the device in reset until V_DD reaches the minimum device operating voltage and re-asserts RST if
V_DD drops below the minimum device operating voltage.
3. Keep the on-chip V_DD Monitor enabled and enable the V_DD Monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V_DD Monitor and enabling the V_DD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Notes:
1. On C8051F99x-C8051F98x devices, both the V_DD Monitor and the V_DD Monitor reset source must be enabled
to write or erase Flash without generating a Flash Error Device Reset.
2. On C8051F99x-C8051F98x devices, both the V_DD Monitor and the V_DD Monitor reset source are enabled by
hardware after a power-on reset.
4. As an added precaution, explicitly enable the V_DD Monitor and enable the V_DD Monitor as a reset
source inside the functions that write and erase Flash memory. The V_DD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
Rev. 1.0
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