C8051F99X_10 Datasheet, PDF (181/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
is enabled and selected as a reset source. The enable state of the V_DD supply monitor and its selection as
a reset source is only altered by power-on and power-fail resets. For example, if the V_DD supply monitor is
de-selected as a reset source and disabled by software, then a software reset is performed, the V_DD
supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as
V_DD does not fall below V_POR. A large capacitor can be used to hold the power supply voltage above V_POR
while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset source select
state of the V_DD supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the V_DD supply falls below the V_WARN threshold. The VDDOK bit can be configured to generate an
interrupt. See Section “13. Interrupt Handler” on page 137 for more details.
Important Note: To protect the integrity of Flash contents, the V_DD supply monitor must be enabled
and selected as a reset source if software contains routines which erase or write Flash memory. If
the V_DD supply monitor is not enabled, any erase or write performed on Flash memory will cause a Flash
Error device reset.
Important Notes:
 The Power-on Reset (POR) delay is not incurred after a V_DD supply monitor reset. See Section
“4. Electrical Characteristics” on page 46 for complete electrical characteristics of the V_DD monitor.
 Software should take care not to inadvertently disable the V_DD Monitor as a reset source when writing
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to 1 to keep the V_DD Monitor enabled as a reset source.
 The V_DD supply monitor must be enabled before selecting it as a reset source. Selecting the V_DD
supply monitor as a reset source before it has stabilized may generate a system reset. In systems
where this reset would be undesirable, a delay should be introduced between enabling the V_DD supply
monitor and selecting it as a reset source. See Section “4. Electrical Characteristics” on page 46 for
minimum V_DD Supply Monitor turn-on time. No delay should be introduced in systems where
software contains routines that erase or write Flash memory. The procedure for enabling the V_DD
supply monitor and selecting it as a reset source is shown below:
1. Enable the V_DD Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the V_DD Supply Monitor to stabilize (optional).
3. Select the V_DD Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
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