C8051F99X_10 Datasheet, PDF (216/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
21.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 21.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
UART0, SPI0, SMBus, CP0
Outputs, System Clock Out-
put, PCA0, Timer0 and
Timer1 External Inputs.
Any pin used for GPIO
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P1.7 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
and SPI1 pins to fixed locations.
P0.0–P1.7, P2.7
SFR(s) used for
Assignment
XBR0, XBR1, XBR2
P0SKIP, P1SKIP
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
External Interrupt 0
External Interrupt 1
Port Match
Potentially Assignable Port Pins
P0.0–P0.7
P0.0–P0.7
P0.0–P1.7
SFR(s) used for
Assignment
IT01CF
IT01CF
P0MASK, P0MAT
P1MASK, P1MAT
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