C8051F99X_10 Datasheet, PDF (139/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
Table 13.1. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable Flag
Priority
Control
Reset
0x0000 Top None
N/A N/A
Always
Enabled
Always
Highest
External Interrupt 0 (INT0) ^{0x0003 0 IE0 (TCON.1)}
Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow
0x000B 1 TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (INT1) ^{0x0013 2 IE1 (TCON.3)}
Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
0x001B 3 TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
UART0
0x0023
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
6
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ET2 (IE.5) PT2 (IP.5)
Y N ESPI0 (IE.6) PSPI0 (IP.6)
SMB0
0x003B 7 SI (SMB0CN.0)
YN
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm
0x0043
8 _{ALRM (RTC0CN.2)}²
NN
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
ADC0 Window Comparator 0x004B 9 AD0WINT (ADC0CN.3)
Y
N
EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
ADC0 End of Conversion 0x0053 10 AD0INT (ADC0CN.5)
YN
EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable Counter
Array
0x005B
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
YN
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0
0x0063
12
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
NN
ECP0
(EIE1.5)
PCP0
(EIP1.5)
Reserved
0x006B 13
Timer 3 Overflow
0x0073
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
NN
ET3
(EIE1.7)
PT3
(EIP1.7)
Supply Monitor Early
Warning
0x007B 15 ^{VDDOK (VDM0CN.5)1}
NN
EWARN
(EIE2.0)
PWARN
(EIP2.0)
Port Match
0x0083 16 None
EMAT
(EIE2.1)
PMAT
(EIP2.1)
SmaRTClock Oscillator Fail 0x008B 17 _{OSCFAIL (RTC0CN.5)}²
NN
ERTC0F
(EIE2.2)
PFRTC0F
(EIP2.2)
Reserved
0x0093 18
CS0 Conversion Complete 0x009B 19 CS0INT (CS0CN.5)
YN
ECSCPT
(EIE2.4)
PCSCPT
(EIP2.4)
CS0 Digital Comparator 0x00A3 20 CS0CMPF (CS0CN.0)
YN
ECSDC
(EIE2.5)
PCSDC
(EIP2.5)
CS0 End of Scan
0x00AB 21 CS0EOS (CS0CN.6)
Y
N
ECSEOS
(EIE2.6)
PCSEOS
(EIP2.6)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
Rev. 1.0
139