C8051F99X_10 Datasheet, PDF (299/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
26.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by
software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while
the CPU is in Idle mode.
Table 26.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0
0
0 _{System clock divided by 12}
0
0
1 _{System clock divided by 4}
0
1
0 Timer 0 overflow
0
1
1 ^{High-to-low transitions on ECI (max rate = system clock divided}
by 4)
1
0
0 _{System clock}
1
0
1
External oscillator source divided by 8¹
1
1
0
SmaRTClock oscillator source divided by 8²
1
1
1
Reserved
Notes:
1. External oscillator source divided by 8 is synchronized with the system clock.
2. SmaRTClock oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
C WW
I DD
DTL
L EC
K
CCCE
PPPC
SSSF
210
PCA0CN
CC
CCC
FR
CCC
FFF
210
SYSCLK/12
000
SYSCLK/4
001
Tim er 0 Overflow
010
ECI
011
SYSCLK
100
External C lock/8
101
S m aR T C lo ck /8
110
PCA0L
read
Snapshot
R e g is te r
To SFR Bus
0
PCA0H
PCA0L
O v e rflo w
To PCA Interrupt System
1
CF
To PCA M odules
Figure 26.2. PCA Counter/Timer Block Diagram
Rev. 1.0
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