C8051F99X_10 Datasheet, PDF (219/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Notes:
1. The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output drivers
are disabled while the Crossbar is disabled.
2. When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be forced
into open-drain output mode regardless of the PnMDOUT setting.
3. SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in
register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is selected. When SPI0 is
selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout of all digital functions lower in
priority than SPI0.
4. For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the device using
Figure 21.3.
5. On 20-pin devices, P1.4 should be skipped in the Crossbar. It is not available as a device pin.
Rev. 1.0
219