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C8051F99X_10 Datasheet, PDF (182/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU
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C8051F99x-C8051F98x
SFR Definition 18.1. VDM0CN: VDD Supply Monitor Control
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT VDDOK
VDDOKIE
Type R/W
R
R
R
R/W
R
Reset
1
Varies Varies
0
1
0
R
R
0
0
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
Function
7
VDMEN VDD Supply Monitor Enable.
This bit turns the VDD supply monitor circuit on/off. The VDD Supply Monitor cannot
generate system resets until it is also selected as a reset source in register RST-
SRC (SFR Definition 18.2).
0: VDD Supply Monitor Disabled.
1: VDD Supply Monitor Enabled.
6 VDDSTAT VDD Supply Status.
This bit indicates the current power supply status.
0: VDD is at or below the VRST threshold.
1: VDD is above the VRST threshold.
5
VDDOK VDD Supply Status (Early Warning).
This bit indicates the current VDD power supply status.
0: VDD is at or below the VDDWARN threshold.
1: VDD is above the VDDWARN threshold.
4
Unused Read = 0b. Write = Don’t Care.
3 VDDOKIE VDD Early Warning Interrupt Enable.
Enables the VDD Early Warning Interrupt.
0: VDD Early Warning Interrupt is disabled.
1: VDD Early Warning Interrupt is enabled.
2:0 Unused Read = 000b. Write = Don’t Care.
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state.
Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of
the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST
pin specifications. The external reset remains functional even when the device is in the low power suspend
and sleep modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The missing clock detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
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Rev. 1.0
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