C8051F99X_10 Datasheet, PDF (218/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
P0
P1
P2
SF Signals
P2.0 - P2.6 not available on
C8051F98x-C8051F99x devices
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
012345670123456701234567
000000000000000000000000
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Port pin assigned to peripheral by the Crossbar
SF Signals Special Function Signals are not assigned by the Crossbar. When
these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
*NSS is only pinned out in 4-wire SPI mode
Note: In this example, CP0, CP0A, and SYSCLK
are not selected in the Crossbar.
Figure 21.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped)
P0
P1
P2
SF Signals
P2.0 - P2.6 not available on
C8051F98x-C8051F99x devices
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
012345670123456701234567
001100001100000000000000
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Port pin assigned to peripheral by the Crossbar
SF Signals Special Function Signals are not assigned by the Crossbar. When
these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
*NSS is only pinned out in 4-wire SPI mode
Note: In this example, CP0, CP0A, and SYSCLK
are not selected in the Crossbar.
Figure 21.5. Crossbar Priority Decoder in Example Configuration (4 Pins Skipped)
218
Rev. 1.0