C8051F99X_10 Datasheet, PDF (124/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
9.4. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding
system function.
SFR Definition 9.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All; SFR Address = 0x82
Bit Name
Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 9.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All; SFR Address = 0x83
Bit Name
Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
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