C8051F99X_10 Datasheet, PDF (231/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
SFR Definition 21.17. P1DRV: Port1 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P1DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA5
Bit Name
Function
7:0 P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
SFR Definition 21.18. P2: Port2
Bit
7
6
5
4
3
2
1
0
Name P2
Type ^R/W
Reset
1
0
0
0
0
0
0
0
SFR Page = All; SFR Address = 0xA0; Bit-Addressable
Bit
Name
Description
Read
Write
7
P2 Port 2 Data.
0: Set output latch to logic 0: P2.7 Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P2.7 Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
6:0 Unused Read = 0000000b; Write = Don’t Care.
Rev. 1.0
231