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C8051F99X_10 Datasheet, PDF (243/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU | |||
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C8051F99x-C8051F98x
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Table 22.3. Sources for Hardware Changes to SMB0CN
Set by Hardware When:
ï® A START is generated.
ï® START is generated.
ï® SMB0DAT is written before the start of an
SMBus frame.
ï® A START followed by an address byte is
received.
ï® A STOP is detected while addressed as a
slave.
ï® Arbitration is lost due to a detected STOP.
ï® A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
ï® A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
ï® SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
ï® SDA is sensed low while transmitting a 1
(excluding ACK bits).
ï® The incoming ACK value is low ï
(ACKNOWLEDGE).
ï® A START has been generated.
ï® Lost arbitration.
ï® A byte has been transmitted and an
ACK/NACK received.
ï® A byte has been received.
ï® A START or repeated START followed by a
slave address + R/W has been received.
ï® A STOP has been received.
Cleared by Hardware When:
ï® A STOP is generated.
ï® Arbitration is lost.
ï® A START is detected.
ï® Arbitration is lost.
ï® SMB0DAT is not written before the
start of an SMBus frame.
ï® Must be cleared by software.
ï® A pending STOP is generated.
ï® After each ACK cycle.
ï® Each time SI is cleared.
ï® The incoming ACK value is high
(NOT ACKNOWLEDGE).
ï® Must be cleared by software.
Rev. 1.0
243
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