C8051F99X_10 Datasheet, PDF (180/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
18.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin voltage tracks V_DD (through a weak
pull-up) until the device is released from reset. After VDD settles above VPOR, a delay occurs before the
device is released from reset; the delay decreases as the V_DD ramp time increases (V_DD ramp time is
defined as how fast V_DD ramps from 0 V to V_POR). Figure 18.2 plots the power-on and V_DD monitor reset
timing. For valid ramp times (less than 3 ms), the power-on reset delay (T_PORDelay) is typically 7 ms (V_DD =
1.8 V) or 15 ms (V_DD = 3.6 V).
Note: The maximum V_DD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before V_DD reaches the V_POR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
The POR supply monitor can be disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit.
When the POR supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the
POR supply monitor.
V_POR
VDD
See specification
table for min/max
voltages.
RST
Logic HIGH
Logic LOW
T_PORDelay
t
T_PORDelay
Power-On
Reset
Power-On
Reset
Figure 18.2. Power-Fail Reset Timing Diagram
18.2. Power-Fail Reset
C8051F99x-C8051F98x devices have a V_DD Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes V_DD to drop below V_RST will cause the RST pin to be
driven low and the CIP-51 will be held in a reset state (see Figure 18.2). When V_DD returns to a level
above V_RST, the CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the V_DD supply monitor
180
Rev. 1.0