C8051F99X_10 Datasheet, PDF (132/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
12.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple-
mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 12.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 12.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs only accessible from Page 0xF are in bold.
The following procedure should be used when accessing SFRs on Page 0xF:
1. Save the current interrupt state (EA_save = EA).
2. Disable Interrupts (EA = 0).
3. Set SFRPAGE = 0xF.
4. Access the SFRs located on SFR Page 0xF.
5. Set SFRPAGE = 0x0.
6. Restore interrupt state (EA = EA_save).
Table 12.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0 B
E8
E0 ACC
D8
D0 PSW
C8
C0
B8
IREF0CF
B0
A8 IE
CLKSEL
A0 P2
98
P0DRV
90 P1
88
80 P0
SP
0(8)
1(9)
(bit addressable)
CS0MD3
REVID DEVICEID
ADC0PWR ADC0TK
CRC0CNT P1DRV CRC0FLIP
DPL
DPH CRC0CN
2(A)
3(B)
4(C)
FLWR
PMU0MD
P2DRV
TOFFL
CRC0IN
5(D)
EIP1
EIE1
CS0PM
EIP2
EIE2
SFRPAGE
CRC0AUTO
TOFFH
CRC0DAT
6(E)
PCON
7(F)
132
Rev. 1.0