C8051F99X_10 Datasheet, PDF (147/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
13.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level
sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active
high or active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 278) select
level or edge sensitive. The table below lists the possible configurations.
IT0 IN0PL
INT0 Interrupt
1
0 Active low, edge sensitive
1
1 Active high, edge sensitive
0
0 Active low, level sensitive
0
1 Active high, level sensitive
IT1 IN1PL
INT1 Interrupt
1
0 Active low, edge sensitive
1
1 Active high, edge sensitive
0
0 Active low, level sensitive
0
1 Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 13.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 217 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external
interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the
corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the
ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active
as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is
inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
Rev. 1.0
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