C8051F99X_10 Datasheet, PDF (55/322 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
Table 4.4. Reset Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
I_OL = 1.4 mA,
V_DD = 2.0 to 3.6 V
V_DD = 0.9 to 2.0 V
V_DD = 2.0 to 3.6 V
V_DD = 0.9 to 2.0 V
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
—
0.6
V
V_DD – 0.6 —
—
V
0.7 x V_DD —
—
V
—
—
0.6
V
—
— 0.3 x V_DD V
—
4
—
µA
—
20
30
VDD Monitor Threshold
(V_RST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8 1.85 1.9
V
1.7 1.75 1.8
VDD Ramp Time for Power
On
VBAT Ramp from 0–1.8 V
—
—
3
ms
POR Monitor Threshold
Brownout Condition (VDD Falling)
0.45 0.7 1.0
(V_POR)
V
Recovery from Brownout (VDD Rising) — 1.75 —
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650 1000
µs
Minimum System Clock w/ _{System clock frequency which triggers}
Missing Clock Detector
a missing clock detector timeout
—
7
10
kHz
Enabled
Reset Time Delay
Delay between release of any reset
source and code
execution at location 0x0000
—
10
—
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
V_DD Monitor Turn-on Time
V_DD Monitor Supply 
Current
—
300
—
ns
—
7
—
µA
Rev. 1.0
55