K4J52324QC Datasheet, PDF (8/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
BLOCK DIAGRAM (2Mbit x 32I/O x 8 Bank)
WDQS
512M GDDR3 SDRAM
Bank Select
iCK
ADDR
Input Buffer
32
Input Buffer
Data Input Register
Serial to parallel
128
LWE
LDMi
2M x 32
2M x 32
2M x 32
2M x 32
2M x 32
2M x 32
2M x 32
2M x 32
128
32
x32
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
LCAS
Programming Register
LWCBR
Timing Register
Output
DLL
CK,CK
LDMi
RDQS
iCK CKE CS RAS CAS WE DMi
-8-
* iCK : internal clock
Rev 1.0 (Mar 2005)