K4J52324QC Datasheet, PDF (28/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
OPERATIONS
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM,
a row in that bank must be "opened." This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued
to that row, subject to the t_RCD specification. t_RCD(min) should be divided by the clock period
and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command in which a READ or WRITE command can be entered. For example, a t_RCD
specification of 16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13.
This is reflected in below figure, which covers any case where 12<t_RCD(min)/t_CK≤ 13.
The same procedure is used to convert other specification limits from tome units to clock
cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after
the previous active row has been "closed"(precharged). The minimum time interval between
successive ACTIVE commads to the same bank is defined by t_RC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row access overhead. The minimum time inter-
val between successive ACTIVE commands to different banks is defined by t_RRD.
/CK
CK
CKE
HIGH
/CS
/RAS
/CAS
/WE
A0-A11
RA
BA0,1,2
BA
RA = Row Address
BA = Bank Address
Activating a Specific Row
in a Specific Bank
Example : Meeting t_RCD
T0
T1
T2
T3
T4
T12
T13
T14
/CK
CK
COMMAND
ACT
NOP
NOP
ACT
NOP
NOP
RD/WR
NOP
A0-A11
Row
Row
Col
BA0~BA2
Bank x
t_RRD
Bank y
t_RCD
Bank y
DON’T CARE
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Rev 1.0 (Mar 2005)