K4J52324QC Datasheet, PDF (6/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
512M GDDR3 SDRAM
Symbol Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi-
tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing). CK and CK should be maintained stable except self-refresh mode.
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buff-
ers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all
banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and
exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selec-
tion on systems with multiple banks. CS is considered part of the command code.
RAS, CAS,
WE
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM0
~DM3
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although
DM pins are input only, the DM loading matches the DQ and WDQS loading.
BA0 ~ BA2
Input
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge com-
mand is being applied.
A0 ~ A11
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank.
A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8
LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2.
The address inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.
DQ0
~ DQ31
Input/
Output
Data Input/ Output: Bi-directional data bus.
RDQS0
~ RDQS3
Output READ Data Strobe: Output with read data. RDQS is edge-aligned with read data.
WDQS0
~ WDQS3
Input WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data.
NC/RFU
No Connect: No internal electrical connection is present.
V_DDQ
V_SSQ
V_DD
V_SS
V_DDA
V_SSA
V_REF
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply
DQ Ground
Power Supply
Ground
DLL Power Supply
DLL Ground
Reference voltage: 0.7*VDDQ ,
2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS
MF
Input Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input.
ZQ Reference Resistor connection pin for On-die termination.
RES
Input Reset pin: RESET pin is a VDDQ CMOS input
SEN
Input Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input.
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Rev 1.0 (Mar 2005)