K4J52324QC Datasheet, PDF (26/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
AUTO PRECHARGE
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without
requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either
enable or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated
at the earliest valid state within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating t_RAS(min), as described for each burst type in the Operation sec-
tion of this data sheet. The user must not issue another command to the same bank until the precharge time(t_RP) is com-
pleted.
AUTO REFRESH
Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR)
REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The
addressing is generated by the internal refresh controller. This makes the address bits a "Don’t Care" during an Auto
Refresh command. The 512Mb(x32) GDDR3 requires Auto Refresh cycles at an average interval of 3.9us (maximum).
A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum
absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This
maximum absolute interval is to allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically recali-
brate compensating for voltage and temperature changes.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is
powered down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automati-
cally disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The
active termination is also disabled upon entering Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles
must then occur before a READ command can be issued). Input signals except CKE are "Don’t Care" during SELF
REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and /CK must be stable
prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands issued for tXSNR
because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh,
DLL requirements and out-put calibration is to apply NOPs for 20K clock cycles before applying any other command to
allow the DLL to lock and the output drivers to recalibrate.
DATA TERMINATOR DISABLE
(BUS SNOOPING FOR READ COMMAND)
The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands
excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators
are disable CL-1 Clocks after the READ command is detected. In a two rank system both dram devices will snoop the bus
for READ commands to either device and both will disable their terminators if a READ command is detected. The com-
mand and address terminators and always enabled.
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Rev 1.0 (Mar 2005)