K4J52324QC Datasheet, PDF (4/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
2M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
• 2.0V + 0.1V power supply for device operation for -BJ** • Single ended READ strobe (RDQS) per byte
• 2.0V + 0.1V power supply for I/O interface for -BJ**
• Single ended WRITE strobe (WDQS) per byte
• 1.8V + 0.1V power supply for device operation for -BC** • RDQS edge-aligned with data for READs
• 1.8V + 0.1V power supply for I/O interface for -BC**
• WDQS center-aligned with data for WRITEs
• On-Die Termination (ODT)
• Data Mask(DM) for masking WRITE data
• Output Driver Strength adjustment by EMRS
• Auto & Self refresh modes
• Calibrated output drive
• Auto Precharge option
• 1.8V Pseudo Open drain compatible inputs/outputs
• 32ms, auto refresh (8K cycle)
• 4 internal banks for concurrent operation
• 136 Ball FBGA
• Differential clock inputs (CK and CK)
• Maximum clock frequency up to 800MHz
• Commands entered on each positive CK edge
• Maximum data rate up to 1.6Gbps/pin
• CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
• DLL for outputs
• Additive latency (AL): 0 and 1 (clock)
• Boundary scan function with SEN pin
• Programmable Burst length : 4 and 8
• Mirror function with MF pin
• Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
ORDERING INFORMATION
Part NO.
K4J52324QC-BJ12
K4J52324QC-BJ14
K4J52324QC-BC14
K4J52324QC-BC16
K4J52324QC-BC20
Max Freq.
800MHz
700MHz
700MHz
600MHz
500MHz
* K4J52324QC-A*** is leaded package part number
Max Data Rate
1.6Gbps/pin
1.4Gbps/pin
1.4Gbps/pin
1.2Gbps/pin
1.0Gbps/pin
VDD&VDDQ
2.0V+0.1V
1.8V+0.1V
Package
136 Ball FBGA
GENERAL DESCRIPTION
FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM
The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized as 8 x 2,097,152 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
-4-
Rev 1.0 (Mar 2005)