K4J52324QC Datasheet, PDF (31/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
READ Burst
T0
T7
/CK
CK
COMMAND
READ
NOP
ADDRESS
RDQS
Bank a,
Col n
CL = 8
DQ
512M GDDR3 SDRAM
T8
T8n
T9
T9n T10
T11
NOP
NOP
NOP
NOP
DO
n
/CK
CK
COMMAND
ADDRESS
RDQS
DQ
T0
T7
READ
NOP
Bank a,
Col n
CL = 9
T8
NOP
T9
T9n T10
NOP
NOP
DO
n
T11
NOP
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DO n=data-out from column n.
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Shown with nominal t_AC and t_DQSQ.
5. RDQS will start driving high 1/2 clock cycle prior to the first falling edge.
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Rev 1.0 (Mar 2005)