K4J52324QC Datasheet, PDF (13/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
CAS LATENCY (READ LATENCY)
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 4~11 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
SPEED
-12
-14
-16
-20
CL=11
≤ 800
CAS Latency
Allowable operating frequency (MHz
CL=10
-
CL=9
-
CL=8
-
CL=7
-
≤ 700
-
-
-
≤ 600
-
-
-
≤ 500
T0
/CK
CK
COMMAND
READ
0
RDQS
DQ
T5
T6
NOP
CL = 7
NOP
T7
T7n
NOP
/CK
CK
COMMAND
RDQS
DQ
T0
READ
T6
T7
NOP
CL = 8
NOP
T8
T8n
NOP
Burst Length = 4 in the cases shown
Shown with nominal t_AC and nominal t_DSDQ
DON’T CARE
TRANSITIONING DATA
- 13 -
Rev 1.0 (Mar 2005)