K4J52324QC Datasheet, PDF (29/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
READs
READ bursts are initiated with a READ command, as below figure. The start-
ing column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto pre-
charge is enabled, the row being accessed is prechrged at the completion of
the burst after t_RAS(min) has been met. For the generic READ commands used
in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column
address will be available following the CAS Latency after the READ com-
mand. Each subsequent data-out element will be valid nominally at the next
positive or negative strobe edge. READ burst figure shows general timing for
2 of the possible CAS latency settings. The GDDR3(x32) drives the output
data edge aligned to the crossing of CK and /CK and to RDQS. The initial
HIGH transitioning LOW of RDQS is known as the read preamble ; the half
cycle coincident with the last data-out element is known as the read postam-
ble.
Upon completion of a burst, assuming no other commands have been initi-
ated, the DQs will go High-Z. A detailed explanation of t_DQSQ (valid data-out
skew), t_DV (data-out window hold), the valid data window are depicted in Data
Output Timing (1) figure. A detailed explanation of t_AC (DQS and DQ transition
skew to CK) is shown in Data Output Timing (2) figure.
Data from any READ burst may be concatenated with data from a subse-
quent READ command. A continuous flow of data can be maintained. The
first data element from the new burst follows the last element of a completed
burst. The new READ command should be issued x cycles after the first
READ command, where x equals the number of data element nibbles (nibbles
are required by the 4n-prefetch architecture) depending on the burst length.
This is shown in consecutive READ bursts figure. Nonconsecutive read data
is shown for illustration in nonconsecutive READ bursts figure. Full-speed
random read accesses within a page (or pages) can be performed as shown
in Random READ accesses figure. Data from a READ burst cannot be termi-
nated or truncated.
During READ commands the GDDR3 Dram disables its data terminators.
512M GDDR3 SDRAM
/CK
CK
CKE _HIGH
/CS
/RAS
/CAS
/WE
A0-A7, A9
CA
A10, A11
A8
BA0,1,2
EN AP
DIS AP
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
READ Command
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Rev 1.0 (Mar 2005)