K4J52324QC Datasheet, PDF (46/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
TRUTH TABLE - Clock Enable (CKE)
CKEn-1
L
L
H
CKEn
L
H
L
CURRENT STATE
Power-Down
Self Refresh
Power-Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
COMMANDn
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
ACTIONn
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
NOTES :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2(x32) immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn
4. All state and sequence not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the t_XSA period.
NOTES
5
- 46 -
Rev 1.0 (Mar 2005)