K4J52324QC Datasheet, PDF (39/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
Consecutive WRITE to WRITE
T0
T1
T2
CK#
CK
COMMAND
WRITE
NOP
WRITE
ADDRESS
WDQS
Bank
Col b
t_DQSS (NOM)
Bank
Col n
DQ
DM
512M GDDR3 SDRAM
T3 T3n T4 T4n T5 T5n T6 T6n T7
NOP
NOP
NOP
NOP
NOP
DI
DI
b
n
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. Burst of 4 is shown.
5. Each WRITE command may be to any bank of the same device.
6. Write latency is set to 3
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Rev 1.0 (Mar 2005)