K4J52324QC Datasheet, PDF (43/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
WRITE to PRECHARGE
T0
T1
T2
T3 T3n T4 T4n T5
/CK
CK
COMMAND
WRITE
NOP
WRITE
NOP
NOP
NOP
ADDRESS
Bank
Col b
Bank
Col b
t_DQSS (NOM)
WDQS
t_DQSS
DQ
DI
b
DM
512M GDDR3 SDRAM
T8
T9
T10
T11
NOP
PRE
NOP
NOP
t_WR
t_RP
Bank
(a or all)
t_DQSS (MIN)
WDQS
t_DQSS
DQ
DI
b
DM
t_DQSS (MAX)
WDQS
t_DQSS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. WRITE latency is set to 3
- 43 -
Rev 1.0 (Mar 2005)