K4J52324QC Datasheet, PDF (41/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
Random WRITE Cycles
T0
T1
/CK
CK
COMMAND
WRITE
NOP
ADDRESS
WDQS
Bank
Col b
t_DQSS (NOM)
DQ
DM
T2
WRITE
Bank
Col x
512M GDDR3 SDRAM
T3 T3n T4 T4n T5 T5n T6 T6n T7
NOP
WRITE
Bank
Col g
NOP
NOP
NOP
DI DI DI DI DI DI DI DI DI DI
b
b
b
b
x
x
x
x
gg
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b, etc. = data-in for column b, etc.
2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order.
3. Programmed burst length = 4 cases shown.
4. Each WRITE command may be to any bank.
5. Last write command will have the rest of the nibble on T8 and T8n
6. Write latency is set to 3
- 41 -
Rev 1.0 (Mar 2005)