K4J52324QC Datasheet, PDF (7/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
Mirror Function
512M GDDR3 SDRAM
The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines
which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F5, H9, F9 and H4
respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11,
M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending
on the control line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS
- F9, CKE - H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0
- G4, BA1 - G9 and BA2 - H10. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS
- F9, RAS - H10, WE - H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11,
A11 - L9, BA0 - G9, BA1 - G4 and BA2 - H3.
PIN
RAS
CAS
WE
CS
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
BA2
Mirror Function Signal Mapping
MF LOGIC STATE
HIGH
LOW
H10
H3
F9
F4
H4
H9
F4
F9
H9
H4
K9
K4
H11
H2
K10
K3
M9
M4
K4
K9
H2
H11
K3
K10
L4
L9
K2
K11
M4
M9
K11
K2
L9
L4
G9
G4
G4
G9
H3
H10
-7-
Rev 1.0 (Mar 2005)