K4J52324QC Datasheet, PDF (55/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
AC CHARACTERISTICS (I-II)
Parameter
DQS out access time from CK
CK high-level width
CK low-level width
CK cycle time
CL=11
CL=10
CL=9
CL=8
CL=7
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
DQS input low pulse widthl
Data strobe edge to Dout edge
DQS read preamble
DQS read postamble
Write command to first DQS latching transition
DQS write preamble
DQS write preamble setup time
DQS write postamble
Half strobe period
Data output hold time from DQS
Data-out high-impedance window
from CK and /CK
Data-out low-impedance window from
CK and /CK
Address and control input hold time
Address and control input setup time
Address and control input pulse width
Jitter over 1~6 clock cycle error
Cycle to cyde duty cycle error
Rise and fall times of CK
Sym-
bol
t_DQSCK
t_CH
t_CL
-BC14
Min
Max
-0.26 +0.26
0.45
0.55
0.45
0.55
t_CK
t_WL
t_DH
t_DS
t_ATS
t_ATH
t_DQSH
t_DQSL
t_DQSQ
t_RPRE
t_RPST
t_DQSS
t_WPRE
t_WPRES
t_WPST
t_HP
t_QH
1.4
1.6
2.0
2.0
5
0.18
0.18
10
10
0.48
0.48
-0.160
0.4
0.4
WL-0.2
0.4
0
0.4
tCLmin or
tCHmin
t_HP-0.16
t_HZ
-0.3
3.3
-
-
-
-
-
0.52
0.52
0.160
0.6
0.6
WL+0.2
0.6
-
0.6
-
-
-
t_LZ
-0.3
-
t_IH
0.35
-
t_IS
0.35
-
t_IPW
1.0
-
tJ
-
0.03
tDCERR
-
0.03
tR, tF
-
0.2
-BC16
Min
Max
-0.29 +0.29
0.45
0.55
0.45
0.55
-
-BC20
Min
Max
-0.35 +0.35
0.45
0.55
0.45
0.55
-
1.6
2.0
2.0
5
0.20
0.20
10
10
0.48
0.48
0.180
0.4
0.4
WL-0.2
0.4
0
0.4
tCLmin or
tCHmin
t_HP-0.18
3.3
-
-
-
-
-
0.52
0.52
0.180
0.6
0.6
WL+0.2
0.6
-
0.6
-
-
-
3.3
-
2.0
4
-
0.25
-
0.25
-
10
-
10
-
0.48
0.52
0.48
0.52
0.225 0.225
0.4
0.6
0.4
0.6
WL-0.2 WL+0.2
0.4
0.6
0
-
0.4
0.6
tCLmin or
tCHmin
-
t_HP-0.225
-
-0.3
-
-0.3
-
-0.3
-
-0.3
-
0.4
-
0.5
-
0.4
-
0.5
-
1.1
-
1.3
-
-
0.03
-
0.03
-
0.03
-
0.03
-
0.2
-
0.2
Unit Note
ns
tCK
tCK
ns
ns
ns
ns
ns
tCK 1
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
tCK 2
ns
tCK 3
tCK
ns
ns 4
ns 4
ns
ns
ns
tCK 5
tCK
tCK
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the
ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks which must be greater than 7ns, the
input buffers are turned on during the WRITE commands for lower power operation.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
5. The cycle to cycle jitter over 1~6 cycle short term jitter
- 55 -
Rev 1.0 (Mar 2005)