K4J52324QC Datasheet, PDF (42/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
WRITE to READ
T0
T1
/CK
CK
COMMAND
WRITE
NOP
ADDRESS
Bank
Col b
t_DQSS (NOM)
WDQS
DQ
DM
RDQS
t_DQSS
T2
WRITE
Bank
Col b
512M GDDR3 SDRAM
T3 T3n T4 T4n T5
T6
T10
T18
T19 T19n
NOP
NOP
NOP
NOP
READ
NOP
NOP
tCDLR = 5
Bank a.
Col n
CL = 8
DI
DI
b
n
t_DQSS (MIN)
WDQS
t_DQSS
DQ
DI
b
DM
RDQS
CL = 8
DI
n
t_DQSS (MAX)
WDQS
t_DQSS
DQ
DI
b
DM
CL = 8
DI
n
RDQS
NOTE :
DON’T CARE
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. t_CDLR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be
to different devices, in which case t_CDLR is not required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. WRITE latency is set to 3
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Rev 1.0 (Mar 2005)