K4J52324QC Datasheet, PDF (14/57 Pages) Samsung semiconductor – 512Mbit GDDR3 SDRAM

K4J52324QC-B
512M GDDR3 SDRAM
WRITE LATENCY
The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of
input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write
latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command
is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved
states should not be used as unknown operation or incompatibility with future versions may result.
/CK
CK
COMMAND
WDQS
DQ
T0
WRITE
T1
T2
NOP
WL = 3
NOP
T3
T3n
NOP
/CK
CK
COMMAND
WDQS
DQ
T0
WRITE
T2
T3
NOP
WL = 4
NOP
T4
T4n
NOP
Burst Length = 4 in the cases shown
DON’T CARE
TRANSITIONING DATA
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Rev 1.0 (Mar 2005)