UPD70F3786GJ-GAE-AX Datasheet, PDF (971/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 20 I²C BUS
20.6 I²C Bus Definitions and Control Methods
The following section describes the I²C bus’s serial data communication format and the signals used by the I²C bus.
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”
generated on the I²C bus’s serial data bus is shown below.
Figure 20-8. I²C Bus Serial Data Transfer Timing
SCL0n
1 to 7 8 9
1 to 8 9
1 to 8 9
SDA0n
Start Address R/W ACK
condition
Data ACK
Data ACK Stop
condition
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-bit
data).
The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin’s
low-level period can be extended and a wait state can be inserted (n = 0 to 2).
Remark n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 971 of 1817