UPD70F3786GJ-GAE-AX Datasheet, PDF (1745/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 35 ELECTRICAL SPECIFICATIONS
(14) RAM retention detection
(TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0, VSS = AVSS = 0 V, CL = 50 pF)
Parameter
Detection voltage
Supply voltage rise time
Response time^Note
Minimum pulse width
Symbol
VRAMH
tRAMHTH
tRAMHD
tRAMHW
Conditions
VDD = 0 to 2.85 V
After VDD reaches 2.1 V
MIN.
TYP.
MAX.
Unit
1.9
2.0
2.1
V
0.002
ms
0.2
3.0
ms
0.2
ms
Note Time required to detect the detection voltage and set the RAMS.RAMF bit.
Supply voltage
(VDD)
Operating voltage (MIN.)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
RAMS.RAMF bit
tRAMHTH
tRAMHD
tRAMHW
tRAMHD
Time
Cleared by instruction
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1745 of 1817