UPD70F3786GJ-GAE-AX Datasheet, PDF (218/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 5 BUS CONTROL FUNCTION
Figure 5-8. Multiplexed/Separate Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
CLKOUT
HLDRQ
HLDAK
A23 to A0^{Note 2}
AD15 to AD0
ASTB
RD
CS3, CS2, CS0^{Notes 3, 4}
T1
T2
T3
TI^{Note 1} TH
TH
TH
TH TI^{Note 1} T1
T2
T3
A1
A1
D1
Undefined
Undefined
1111
Undefined
A2
Undefined A2
D2
1111
Notes 1. This idle state (TI) does not depend on the BCC register settings.
2. V850ES/JJ3-E only. The A21 to A0 pins are used in the V850ES/JH3-E.
3. V850ES/JJ3-E only. The CS2 and CS0 pins are used in the V850ES/JH3-E.
4. Only the CS space subject to access is active.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
2. The broken lines indicate the high-impedance state.
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 218 of 1817