UPD70F3786GJ-GAE-AX Datasheet, PDF (1376/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 23 ETHERNET CONTROLLER
(4) IPGR: Non back-to-back IPG register
Access
This register can be read and written in 32-bit units.
Address
002E 000CH
Default value 0000 0E13H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 15 and 7 to “0”.
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
0
IPGR1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
IPGR2
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
14 to 8
6 to 0
Name
IPGR1
IPGR2
Description
Carrier sense period
These bits set the carrier sense period of the first half of the IPG in transmission other than back-to-
back transmission. The calculation expression used to calculate the carrier sense period is as
follows.
• Carrier sense period = (2 + IPGR1) x time required to transmit 4 bits
Set the carrier sense period to 2/3IPG to satisfy the specification of IEEE802.3 (refer to 23.5.2 (5)
Inter-packet gap (IPG)).
IPG in transmission other than back-to-back transmission
These bits set the IPG in transmission other than back-to-back transmission. The expression used
to calculate the IPG is as follows.
• IPG = (5 + IPGR2) x time required to transmit 4 bits
The carrier sense period set by IPGR1 is included in the IPG set by IPGR2. Set the IPG to the time
required to transmit at least 96 bits to satisfy the specification of IEEE802.3 (refer to 23.5.2 (5)
Inter-packet gap (IPG)).
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1376 of 1817