UPD70F3786GJ-GAE-AX Datasheet, PDF (223/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 6 CLOCK GENERATION FUNCTION
After reset: 03H R/W Address: FFFFF828H
PCC
FRC
<>
MCK
MFRC
<>
CLS^Note
<>
CK3
CK2
CK1
CK0
FRC
0
1
Used
Not used
Use of subclock on-chip feedback resistor
MCK
Main clock oscillator control
0 Oscillation enabled
1 Oscillation stopped
• Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
• Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
• When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
MFRC
0 Used
1 Not used
Use of main clock on-chip feedback resistor
CLS^Note
0 Main clock operation
1 Subclock operation
Status of CPU clock (fCPU)
CK3
0
0
0
0
0
0
0
1
CK2
0
0
0
0
1
1
1
×
CK1
0
0
1
1
0
0
1
×
CK0
0
1
0
1
0
1
×
×
Clock selection (fCLK/fCPU)
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
Setting prohibited
fXT
Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
output.
2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Remark ×: don't care
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 223 of 1817