UPD70F3786GJ-GAE-AX Datasheet, PDF (863/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
(3) Data transfer direction specification function
The data transfer direction can be changed by using the CEnCTL0.CEnDIR bit (n = 0, 1).
(a) MSB first (CEnDIR bit = 0)
Figure 18-4. Transfer Data Length: 8 Bits (CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 bits = 1000),
Transfer Direction: MSB First (CEnCTL0.CEnDIR bit = 0) (1/2)
SCKEn (I/O)
SIEn (input)
SOEn (output)
(i) Transfer direction: MSB first
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
(ii) Writing from CEnTX0 register to CSIBUFn register
15
87
0
CEnTX0
CSIBUFn
Data
00H
SOEn
Remark n = 0, 1
SIOn
SIEn
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 863 of 1817