UPD70F3786GJ-GAE-AX Datasheet, PDF (1249/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
(31) UF0 data end register (UF0DEND)
This register reports the end of writing to the transmission system.
This register can be read or written in 8-bit units.
FW can start data transfer of the target endpoint by writing 1 to the corresponding bit of this register. The bit to
which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7)
and the current setting of the interface.
(1/2)
7
6
5
UF0DEND BKI2T BKI1T
0
4
3
2
1
0
Address After reset
0 IT1DEND BKI2DED BKI1DED E0DED 0020006AH
00H
Bit position
7, 6
Bit name
BKInT
3
IT1DEND
Function
These bits specify whether toggling the FIFO is automatically executed if the FIFO on the
CPU side of the UF0BIn register becomes full as a result of DMA.
1: Automatically execute a toggle operation of the FIFO as soon as the FIFO has
become full.
0: Do not automatically execute a toggle operation of the FIFO even if the FIFO
becomes full (default value).
Set these bits to 1 to transmit the data of the UF0INT1 register. When these bits are set
to 1, the IT1NK bit is set to 1 and data transfer is executed.
1: Transmit a short packet.
0: Do not transmit a short packet (default value).
If the ITR1C bit of the UF0FIC0 register is set to 1 and then these bits are set to 1
(counter of UF0INT1 register = 0 and the corresponding bit of the UF0EPS0 register = 1),
a Null packet (with a data length of 0) is transmitted.
If data exists in the UF0INT1 register and if these bits are set to 1 (counter of UF0INT1
register ≠ 0 and the corresponding bit of the UF0EPS0 register = 1), a short packet is
transmitted.
These bits are automatically controlled by hardware when the FIFO is full.
Remark n = 1, 2
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1249 of 1817