UPD70F3786GJ-GAE-AX Datasheet, PDF (371/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
8.5.1 Interval timer mode (TABnMD2 to TABnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTABnCC0) is generated at the specified interval if the
TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0
pin.
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode.
Figure 8-2. Configuration of Interval Timer
Count clock
selection
TABnCE bit
Clear
16-bit counter
Match signal
CCR0 buffer register
Output
controller
TOABn0 pin
INTTABnCC0 signal
Remark n = 0, 1
TABnCCR0 register
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
Remark n = 0, 1
D0
D0
D0
D0
D0
Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1)
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 371 of 1817