UPD70F3786GJ-GAE-AX Datasheet, PDF (1733/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 35 ELECTRICAL SPECIFICATIONS
(7) CSIF timing
(a) Master mode
[When using CSIF3, CSIF4 (Port DH pins), CSIF5, CSIF6 (8.33 MHz)]
(TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0, VSS = AVSS = 0 V, CL =30 pF)
Parameter
SCKFn cycle time
SCKFn high-level width
SCKFn low-level width
SIFn setup time (to SCKFn↑)
SIFn setup time (to SCKFn↓)
SIFn hold time (from SCKFn↑)
SIFn hold time (from SCKFn↓)
SOFn output delay time (from SCKFn↑)
SOFn output delay time (from SCKFn↓)
SOFn output hold time (from SCKFn↑)
SOFn output hold time (from SCKFn↓)
Symbol
tKCY1 <69>
tKH1 <70>
tKL1
tSIK1 <71>
tKSI1 <72>
tKSO1 <73>
tHSO1 <74>
Conditions
MIN.
MAX.
Unit
120
ns
tKCY1/2 − 8
ns
tKCY1/2 − 8
ns
26
ns
26
ns
26
ns
26
ns
26
ns
26
ns
tKCY1/2 − 10
ns
tKCY1/2 − 10
ns
Remark n = 3 to 6
[When using CSI4 (Port DH pins side) (12.5 MHz)]
(TA = −40 to +85°C, VDD = EVDD = UVDD = AVREF0, VSS = AVSS = 0 V, CL = 30 pF)
Parameter
SCKF4 cycle time
Symbol
tKCYM <69>
Conditions
MIN.
80
MAX.
Unit
ns
SCKF4 high-level width
tKHM <70>
tKCYM/2 − 8
ns
SCKF4 low-level width
tKCYM/2 − 8
ns
SIF4 setup time (to SCKF4↑)
tSIKM <71>
19
ns
SIF4 setup time (to SCKF4↓)
19
ns
SIF4 hold time (from SCKF4↑)
tKSIM <72>
13
ns
SIF4 hold time (from SCKF4↓)
13
ns
SOF4 output delay time (from SCKF4↑) tKSOM <73>
13
ns
SOF4 output delay time (from SCKF4↓)
13
ns
SOF4 output hold time (from SCKF4↑) tHSOM <74>
tKCYM/2 − 10
ns
SOF3 output hold time (from SCKF4↓)
tKCYM/2 − 10
ns
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1733 of 1817