UPD70F3786GJ-GAE-AX Datasheet, PDF (1375/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 23 ETHERNET CONTROLLER
(3) IPGT: Back-to-back IPG register
Access
This register can be read and written in 32-bit units.
Address
002E 0008H
Default value 0000 0013H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 7 to “0”.
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
IPGT
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
6 to 0
Name
IPGT
Description
IPG in back-to-back transmission:
These bits set the gap between packets (or an inter-packet gap (IPG)) in back-to-back
transmission. The expression used to calculate IPG is as follows.
• IPG = (5 + IPGT) x time required to transmit 4 bits
(Time required to transmit 1 bit = 100 ns when the data rate is 10 Mbps or 10 ns when the data
rate is 100 Mbps)
Set IPG to the time required to transmit at least 96 bits to satisfy the specification of IEEE802.3
(refer to 23.5.2 (5) Inter-packet gap (IPG)).
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1375 of 1817