UPD70F3786GJ-GAE-AX Datasheet, PDF (304/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(c) Generation timing of compare match interrupt request signal (INTTAAnCC1)
The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other
INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of
the 16-bit counter matches the value of the TAAnCCR1 register.
Count clock
16-bit counter
D1 − 2
D1 − 1
D1
D1 + 1
D1 + 2
TAAnCCR1 register
D1
TOAAn1 pin output
INTTAAnCC1 signal
Remark n = 0 to 5
Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up after the count value of
the 16-bit counter matches the value of the TAAnCCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to
match the change timing of the output signal of the TOAAn1 pin.
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 304 of 1817