UPD70F3786GJ-GAE-AX Datasheet, PDF (933/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← A3H
CFnRX register
(4)
dummy read
(4)
SCKFn pin input
No
started?
Yes
(5)
Reception start
No
INTCFnR interrupt
generated?
Yes
CFnOVE bit = 1?
No
(6)
(CFnSTR)
Yes
CFnSCE bit = 0
(8)
(CFnCTL0)
(9)
Read CFnRX register
(12)
CFnOVE bit = 0
(CFnSTR)
Is data being received
No
last data?
Yes
CFnSCE bit = 0
(8)
(CFnCTL0)
(9)
Read CFnRX register
(7)
(9)
Read CFnRX register
(10)
INTCFnR interrupt
No
generated?
Yes
(11)
Read CFnRX register
(13)
CFnTSF bit = 0?
No
(CFnSTR)
Yes
(13) CFnCTL0 register ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 933 of 1817