UPD70F3786GJ-GAE-AX Datasheet, PDF (1646/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 30 LOW-VOLTAGE DETECTOR (LVI)
30.4 Operation
Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated.
How to specify each operation is described below, together with timing charts.
30.4.1 To use for internal reset signal
<To start operation>
<1> Mask the interrupt of LVI.
<2> Set the LVIM.LVION bit to 1 (to enable operation).
<3> Insert a wait cycle of 0.2 ms (max.) or more by software.
<4> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage.
<5> Set the LVIMD bit to 1 (to generate an internal reset signal).
Caution If the LVIMD bit is set to 1, the contents of the LVIM register cannot be changed until a reset request
other than LVI is generated.
Figure 30-2. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1)
Supply voltage (VDD)
LVI detected voltage
(2.95 V (TYP.))
LVION bit
LVI detected signal
Delay
LVI reset request signal
Internal reset signal
(active low)
Clear
Time
Delay
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1646 of 1817