UPD70F3786GJ-GAE-AX Datasheet, PDF (342/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
7.8 Cascade Connection
This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer.
For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as
capture registers (TAA0CCSn = 1).
Combinations of TAA channels that can be connected in cascade are shown in the following table.
Table 7-11. Cascade Connection of TAA
Lower Timer (Master Timer)
TAA1
TAA3
Higher Timer (Slave Timer)
TAA0
TAA2
In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave
timer) to use them as a 32-bit capture timer by cascade connection.
Figure 7-50. Cascade Connection Example
[Lower timer TAA1]
Lower capture interrupt 1
(INTTAA1CC1)
Capture signal 1
(TIAA11)
Edge
detection
Count
clock
selection
Operation enable
bit (TAA1CE)
Lower capture register 1
(TAA1CCR1)
Lower timer counter
FFFFH
detection
signal
Lower capture register 0
(TAA1CCR0)
Capture signal 0
(TIAA10)
Edge
detection
Lower capture interrupt 0
(INTTAA1CC0)
Lower overflow interrupt
(INTTAA1OV)
[Higher timer TAA0]
Higher capture register 1
(TAA0CCR1)
Higher timer counter
Higher capture register 0
(TAA0CCR0)
Higher overflow interrupt
(INTTAA0OV)
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 342 of 1817