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| UPD70F3786GJ-GAE-AX Datasheet, PDF (1022/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers | |||
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V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 20 I2C BUS
Figure 20-24. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
Processing by master device
IICn
IICn â data Note 1
(b) Data
ACKDn
STDn L
SPDn L
WTIMn H
ACKEn H
MSTSn H
STTn L
SPTn L
WRELn L
INTIICn
TRCn H Transmit
Transfer lines
SCL0n 8 9
123456789
SDA0n D0 ACK
D7 D6 D5 D4 D3 D2 D1 D0 ACK
IICn â data Note 1
123
D7 D6 D5
Processing by slave device
IICn
IICn â FFH Note 2
IICn â FFH Note 2
ACKDn
STDn L
SPDn L
WTIMn H
ACKEn H
MSTSn L
STTn L
SPTn L
WRELn
Note 2
Note 2
INTIICn
TRCn L Receive
Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn.
2. To cancel the slave wait state, write FFH to IICn or set WRELn.
Remark n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1022 of 1817
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